An ALU (Arithmetic Logic Unit) is a digital electrical circuit that performs arithmetic and bitwise logical operations on binary values. It works with binary numbers in terms of individual bits, while arithmetic procedures deal with numbers. Here I have designed a 4-bit ALU who will perform different operations like addition, equality of inputs, right shift, 1’s compliment and bit-wise and.
Parameters:
A => Input 1 (4 Bit)
B => Input 2 (4 Bit)
Select => Selects the
operation (3 Bit)
Out => ALU output,
depends on select pin
Overflow => For addition
there might be carry, extra bit pin will show that output
Select Pin Operations:
000: Addition
001: Check Equality of 4-bit
inputs
010: Right Shifts input 1
011: 1’s Compliment of input 2
100: Bit-wise AND
101, 110, 111: Default
Operations:
|
Select |
Operation |
Output Logic |
|
000 |
Addition |
A + B |
|
001 |
Equality of Inputs |
A == B |
|
010 |
Right Shift of Input 1 |
A >> 1 |
|
011 |
1’s Compliment of Input 2 |
~B |
|
100 |
Bit-wise AND |
A & B |
|
101 |
No Operation |
0 |
|
110 |
No Operation |
0 |
|
111 |
No Operation |
0 |
Verilog Code:
input wire [3:0] A,
input wire [3:0] B,
input wire [2:0] select,
output wire [3:0] out,
output wire overflow
);
integer i;
reg [4:0] inter_out;
reg inter_overflow;
always @ (*)
begin
case (select)
// Addition
3'b000:
begin
inter_out = A + B;
inter_overflow = inter_out[4];
end
// Check if the inputs are equal
3'b001:
begin
if (A == B)
begin
inter_out [3:0] = 4'b1111;
{inter_out [4] , inter_overflow} = 0;
end
else
inter_out [3:0] = 0;
{inter_out [4] , inter_overflow} = 0;
end
// Right shifts input 1
3'b010:
begin
inter_out [3:0] = A>>1;
{inter_out [4] , inter_overflow} = 0;
end
// 1's compliment of the bits of input 2
3'b011:
begin
for (i = 0; i<4; i = i+1)
begin
if (B[i] == 0)
begin
inter_out[i] = 1;
{inter_out [4] , inter_overflow} = 0;
end
else
begin
inter_out[i] = 0;
{inter_out [4] , inter_overflow} = 0;
end
end
end
// Bit wise AND
3'b100:
begin
inter_out [3:0] = A & B;
{inter_out [4] , inter_overflow} = 0;
end
// Default cases {101, 110, 111}
default:
{inter_out, inter_overflow} = 0;
endcase
end
assign out = inter_out;
assign overflow = inter_overflow;
endmodule
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