VLSI: Basic Question And Answers

VLSI: Basic Question & Answers covers questions about basic vlsi knowledge, design for testability basics, verilog codes, testbenches, basic of git, perforce, python file handling, tool command language, tcl and different vlsi industry based queries and tries to answer them.

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VLSI Basics

How Two Level Sensitive D Latch Makes An Edge Sensitive D Flip Flop | VLSI Basics

Adnan Mohammed OsmanOctober 13, 2021

Here two level sensitive D latch works as an edge sensitive D flipflop. The agenda of this post is to understand how the circuit in the left of the diagram works as a D flipflop. We can see a D latch has 2 input pins, Din and Enable. Din is the…

Simulation Using ModelSim Commands

October 16, 2022

Step 1: Setup Create a new project from File. Set the Project Location and Project Name. Click the Add Existing Fi…

Testbench for "4-bit Addition, But With A Twist" Problem | Verilog Code | VLSI

June 27, 2022

To see the actual design problem, please go through the 4-bit Addition, But With A Twist post. Now we will write a simp…

4-bit Addition, But With A Twist! | Verilog Code | VLSI

June 21, 2022

Question Take a random 8-bit input. The output is 5 bits [output sequence 4-bit and 1-bit extra]. If there are even num…

Synopsys Design Constraints (SDC)

February 04, 2022

What is SDC? SDC is a format that is used to specify the design intent, which includes timing, power and area constrain…

Quadratic Equation Solver Using TCL

January 22, 2022

Basic Quadratic Equation Format: ax^2 + bx + c = 0, where a ≠ 0 Formula: The (b^2 - 4ac) part is called the discrimi…

Full Subtractor Verilog Code | VLSI

December 04, 2021

Verilog Code: module full_sub (A, B, C, D, Borrow); input A, B, C; output D, Borrow; wire b1, b2; half_sub …

Half Subtractor Verilog Code | VLSI

December 04, 2021

Circuit of Half Subtractor: Verilog Code: module half_sub( A, B, D, Borrow); input A,B; output D, Borrow; assign …

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