At first we should know what is reset? The reset input resets the flip-flop back to its original state with an output Q that will be either at a logic level “1” or logic “0” depending upon this set/reset condition. To reset a flop we can give either 1 or 0 depending on the design. As D flip-flops are much commonly used I am going to use them as as example. There are two types of reset,
- Active Low Reset
- Active High Reset
Active Low Reset: From the name we can guess, when the reset signal is low the flop is reseted. Now we have to understand what will happen if we pass 0 or 1 as reset. For an active low reset design if we pass 0 then the output Q will become 0 and if we pass 1 then D will be passed to Q.
Reset 0 => Flop Reseted
Reset1 => Functional Mode
Verilog Example:
always @ (posedge clk)
if (!reset) // Checking if value of reset is 0
q <= 1'b0; // If reset is 0 set Q to 0
else
q <= D // If reset is 1 set Q to D
Active High Reset: From the name we can guess, when the reset signal is high the flop is reseted. For an active high reset design if we pass 1 then the output Q will become 0 and if we pass 0 then D will be passed to Q.
Reset 0 => Functional Mode
Reset 1 => Flop Reseted
Verilog Example:
always @ (posedge clk)
if (reset) // Checking if value of reset is 1
q <= 1'b0; // If reset is 1 set Q to 0
else
q <= D // If reset is 0 set Q to D
Note:
The active low reset or active high reset will depend on your design specs or client requirement. So, while designing we have to keep in mind about the change for both 0 and 1 in the reset pin.
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