A deep submicron devices contain a large number of memories which demands lower area and fast access time, hence an automated test strategy for such designs is required to reduce ATE (Automatic Test Equipment) cost and testing time. Conventional DFT methods do not provide a complete solution to the requirement of testing memory faults and its self-repair capabilities. A promising solution is Memory Built In Self Test (MBIST). To test the memories functionality ATPG is required to be very large external pattern sets for acceptable test coverage due to the size density of the cell array and its associated faults.
Before going to the
operations of MBISR, here is a simplistic diagram of a 2D memory organization.
There are rows and columns which is called the word line and bit line
respectively.
Here is an example,
we can see a fault has occurred on the 5th row and 3rd column. What MBISR does, it replaces those faulty cells with the backup cells.
We can see after the replacement the previous 6th row has become the
new 5th row. Same goes for the column. MBISR replaces the faulty
column with the backup column so the functionality is undisturbed.
BISR Chain:
The Built In Self Repair (BISR) logic insertion tasks are as follows:
- Create BISR chains in design
- Connect BISR controller to chain
- BISR controller will be connected to e-fuse box
- BISR controller to logic connection will be created
Challenges with enabling BISR:
- Additional area overhead
- Scannable flops inserted for repair
- Increment in pin count
- Higher run time
- Pattern inflation during ATPG
See also: Memory Built in Self Test (MBIST)
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