Testbench for "4-bit Addition, But With A Twist" Problem | Verilog Code | VLSI

To see the actual design problem, please go through the 4-bit Addition, But With A Twist post. Now we will write a simple test-bench, simulated our design and see the waveforms. But at first, what is a test-bench?

Test-bench

A test-bench is just another name for a System Verilog module. It is not, however, the same as the Verilog code we write for a DUT (Design Under Test). Because the design's Verilog code is what we use to plan our hardware, it must be synthesizable. In contrast, a test-bench module does not need to be synthesizable. Its sole objective is to verify that our design meets the specified standards.

Code

`include "half_adder.v"
`include "fulladder.v"
module test;

  logic [4:0] out;
  logic [7:0] val;
  logic clk;
  logic reset;
  logic enable;
  
  verilog_test DUT (
    .out(out),
    .val(val),
    .clk(clk),
    .reset(reset),
    .enable(enable)
  );
  
  initial begin
  	// Dump waves
  	$dumpfile("dump.vcd");
    $dumpvars(1);
    clk=1;
  end
    
  always begin
    #5 clk = ~clk;
  end
  
  initial 
	begin
		val = 8'b00000000;
      	reset=1'b0;
      	enable=1'b0;
	end
  
  initial
    begin
      #15 enable = 1'b1;
      #20 reset = 1'b1;
      val = 8'b00110101;
      #50 val = 8'b10110100;
      #45
      $finish;
    end
endmodule

Waveform