Full Subtractor Verilog Code | VLSI

Verilog Code:

module full_sub (A, B, C, D, Borrow);

input A, B, C;

output D, Borrow;

wire b1, b2;

half_sub h1 (A, B, d1, b1);                    //Calling my half_sub module and naming it h1

half_sub h2 (C, d1, D, b2);                    //Calling my half_sub module and naming it h2

assign Borrow = b1 | b2;

endmodule