Testbench For 4 Bit ALU | Verilog Code | VLSI

 A testbench is simply a System Verilog module.  However, it is not the same as the Verilog code we create for a DUT (Design Under Test). Since the Verilog code of the design is what we use for planning our hardware, it must be synthesizable. A testbench module, on the other hand, does not have to be synthesizable. It’s only purpose is to test the desired specifications of our design.

This is a testbench for the 4 bit ALU I have designed before. To read the operations of our designed 4 Bit ALU, you can click here.

System Verilog Code:

module tb_ALU();
                bit tb_clk;
                logic [3:0] tb_A;
                logic [3:0] tb_B;
                logic [2:0] tb_select;
                logic [3:0] tb_out;
                logic tb_overflow;
 
                ALU DUT (
                                .A(tb_A),
                                .B(tb_B),
                                .select(tb_select),
                                .out(tb_out),
                                .overflow(tb_overflow)
                );
 
                // Clock Generation
                initial forever
                begin
                                #5ns tb_clk = ~tb_clk;
                end
 
                // Value initialization
                initial
                begin
                                tb_clk = 0;
                                tb_A = 4'b0000;
                                tb_B = 4'b0000;
                                tb_select = 3'b000;
                                tb_out = 4'b0000;
                                tb_overflow = 0;
                end
 
                // VCD generation
                initial
                begin
                                $dumpfile("ALU.vcd");
                                $dumpvars();
                end
 
                // Simulation run time
                initial
                begin
                                #125ns
                                $stop;
                end
 
                always @ (posedge tb_clk)
                begin
                                tb_A = $urandom;
                                tb_B = $urandom;
                                tb_select = 3'b000; #10ns;
                                tb_select = 3'b001; #10ns;
                                tb_select = 3'b010; #10ns;
                                tb_select = 3'b011; #10ns;
                                tb_select = 3'b100; #10ns;
                                tb_select = 3'b111; #10ns;           
                end
 
endmodule

See also: 4 Bit ALU Design