Full Scan Design With Muxed D Scan Cell

In full-scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers (also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed.

The main advantage of full-scan design is that it converts the difficult problem of sequential ATPG into the simpler problem of combinational ATPG.

Previously In the SCOAP post, we have used a circuit to demonstrate how to calculate controllability and observability for a circuit. We will now convert the circuit to a full scan design with Muxed D scan cell,

So, the modified full-scan design with muxed D scan cell of the circuit is, 

Now, if we want to pass a test vector 010, we have to serially input the vector. When SE is high it will work as a shift register, shifting the values we give. Here I have given the test vector 010 which is the Pseudo Primary Input, A, B and C of the circuit. The LSB is passed at first and MSB at last. When SE is low, it will work in capture mode. As the test vector 010 will create a series of Pseudo Primary Output, Y, Z and X. And from the truth table, we can verify for which leaf the fault has occurred. We can cross check with it and come to a decision.

Now when SE is again high, It will shift the captured values X, Z and Y and we can see them in the output. We can see this more clearly in the waveform.

See also: SCOAP, Scan architectures, Controllability & observability, Muxed D scan cell, Partial scan design, Random access scan design