Muxed D Scan Cell Design

The structured DFT approach attempts to improve the overall testability of a circuit with  a test-oriented design methodology. This approach is methodical and systemic and with much ore predictable results. 

Scan design, the most widely used structured DFT methodology, attempts to improve testability of a circuit by improving the controllability and observability of storage elements in a sequential design. Typically this is accomplished by converting the sequential into a scan design with three modes of operation: normal mode, shift mode, and capture mode. This is also the solution that we have discussed in the previous Ad hoc approach of Test point Insertion (TPI) post.  

Scan Cell Design

In a scan cell, the input data is driven by combinational logic of a circuit. Scan input is driven by the output of another scan cell to from a chain with one or more shift registers, which is called a scan chain. The scan input of the first scan cell is connected to the primary input and scan output of the last scan cell is connected to the primary output. In normal/capture mode, data input is selected to update the output. In the shift mode, scan input is selected to update the output. This makes it possible to shift in an arbitrary test pattern to all scan cells from one or more primary inputs while shifting out the contents of all scan cells through one or more primary outputs.

    Muxed D Scan Cell:

This type of scan cell is composed of a D flip-flop and a multiplexer. The multiplexer uses a scan enable (SE) input to select between the data input (DI) and the scan input (SI).

In normal/capture mode, SE is set to 0. The value present at the data input DI is captured into the internal D flip-flop when the clock has a positive or rising edge. In shift mode, SE is set to 1. The SI is now used to shift in new data to the D flip-flop while the content of the D flip-flop is being shifted out. 

From the graph we can see when SE in 0, Q/SO is the output of what DI is at the positive edge. The output holds out until it finds another positive edge. In the next positive edge it sees SE is 1, so it will operate in shift mode and pass the SI data of that positive edge. 

A level-sensitive and edge-triggered muxed D scan cell design can be used to replace a D flip-flop in a scan design. The scan cell is composed of a multiplexer, a D latch and a D flip-flop. In this case, shift operation is conducted in an edge-triggered manner while normal operation and capture operation are conducted in a level sensitive manner. 

But in the industry this design is not used as there are hundreds and thousands of flip-flops in a design and adding an extra latch will add un-necessary area to the design. So we change the flip-flops to the Muxed D scan cell which is described earlier. 

See Also: Ad hoc approach, TPI, Testability analysis