What is TPI?
Test Point Insertion (TPI) is a commonly used Ad hoc DFT technique for improving the controllability and observability of internal nodes. There are normally two approaches or techniques in DFT, one is the Ad hoc approach and the other is the Structured approach.
Testability of combinational logic decreases as the level of combinational logic increases. For sequential circuit, it is a bit more difficult to improve good testability. Hence, a more structured approach for testing designs that contain a large amount of sequential logic is required as part of a methodical design for DFT testability approach.
Testability analysis is typically used to identify the internal nodes where the test point should be inserted or TPI can be performed in the form of control or observation points.
Observation Point Insertion:
This is an example of observation point insertion for a logic circuit with three low observability nodes. OP2 shows the structure of an observation point that is composed of a multiplexer (MUX) and a D flip-flop. A low-observability node is connected to the 0 port of the MUX in an observation point, and all observation points are serially connected into an observation shift register using the 1 port of the MUX. An SE signal is used for MUX port selection. When SE is set to 0 and the clock CK is applied, the logic values of the low-observability nodes are captured into the D flip-flops. When SE is set to 1, the D flip-flops within OP1, OP2, and OP3 operate as a shift register, allowing us to observe the captured logic values through OP_output during sequential clock cycles. As a result, the observability of the circuit nodes is greatly improved.
Control Point Insertion:
This is an example of control point insertion for a logic circuit with three low-controllability nodes. CP2 shows the structure of a control point (CP) that is composed of a MUX and a D flip-flop. The original connection at a low controllability node is cut, and a MUX is inserted between the source and destination ends. During normal operation, the test mode (TM) is set to 0 so that the value from the source end drives the destination end through the 0 port of the MUX. During test, TM is set to 1 so that the value from the D flip-flop drives the destination end through the 1 port of the MUX. The D flip-flops in OP1, OP2, and OP3 are designed to form a shift register so the required values can be shifted into the flipflops using CP_input and used to control the destination ends of low-controllability nodes. As a result, the controllability of the circuit nodes is dramatically improved.
These observation point and control point insertion, however, results in additional delay to the logic path. Hence, care must be taken not to insert control points on a critical path. Furthermore, it is preferable to add a scan point, which is a combination of a control point and an observation point, instead of a control point, as this allows us to observe the source end as well.
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