Testability Analysis

At first, we should know what is testability. Testability is the ability to put a design into a known initial state, and then control and observe internal signal values. It reflects the effort required to perform the main test operations of controlling internal signals from primary inputs and observing internal signals at primary outputs. 

Testability analysis refers to the process of assessing the testability of a logic circuit by calculating a set of numerical measures for each signal in the circuit. By doing this, we can easily understand if we can access any fault that has occurred in any point of a circuit or not. There are different methods to analyze the testability of a circuit,

• Topology based 
• SCOAP (Sandia Controllability/Observability Analysis Program)
• Probability based
• Simulation based
• RTL testability analysis

The Sandia Controllability/Observability Analysis Program (SCOAP) was the first topology-based program that popularized testability analysis applications. Topology based or probability-based testability analysis is computationally efficient but may produce inaccurate results, whereas simulation-based testability analysis produces more accurate results & it requires long simulation time. RTL testability analysis is simply too complex, so it will be out of context for our discussion.

See Also: SCOAP, Probability based analysis, SCOAP vs Probability based testability analysis, Simulation based analysis