Delay Faults & Crosstalk

Delay Faults

With decreasing feature sizes and increasing signal speeds, the problem of modeling gate delays becomes more difficult. A delay fault occurs when the time interval taken for a transition from the gate input to its output exceeds its specified range. It causes excessive delay along a path such that the total propagation delay falls outside the specified limit.

Due to delay fault the transition at the output y will occur at some later time at t > 7.

Crosstalk

The use of nanometer technologies increases cross-coupling capacitance and inductance between interconnects, leading to severe crosstalk effects that may result in improper functioning of a chip. The lateral capacitance between nets/wires on silicon becomes significantly more dominating than the interlayer capacitance in deep sub-micron technology. As a result, the nets have a capacitive coupling, which can cause logic errors and timing deterioration in VLSI circuits. Crosstalk is a phenomena caused by capacitive coupling, in which logic carried in a VLSI circuit or a net/wire has an unintended influence on nearby circuits or nets/wires.

See also: Stuck at faults, Transistor faults, Bridging faults