What Are Stuck At Faults in VLSI Digital Circuit Design?

What Are Stuck At Faults

When a line is permanently connected to Vdd or ground, a stuck at fault occurs, resulting in an erroneous output. Any gate can use this line as an input or output. The signal is said to be "stuck at" when it is trapped at a 0 or 1 value regardless of the circuit's inputs, and the fault model used to explain this type of error is called a "stuck at fault model." If a circuit includes n signal lines, the circuit could have up to 2n stuck-at problems. 

The test vector is a set of bits that should be applied to the circuit's inputs and a set of bits that should be expected at the circuit's output. Because no delay information is linked with the problem definition, the stuck-at fault model is a logical fault model. Because it is based on a structural gate-level circuit model, the single stuck-at fault model is structural. 

Tests to detect every potential stuck-at fault in a circuit make up a pattern set with 100% stuck-at fault coverage. Because many other types of problems, such as bridging faults, openings faults, and transition or delay faults, frequently occur, 100% stuck-at fault coverage does not guarantee excellent quality.

How To Generate Efficient Test Patterns To Detect All Stuck At Faults

For example, if we look at the circuit we can see it has 3 inputs x1, x2, x3 and one output y. 
 
There are 2 X 9 = 18 possible faults under the single fault assumption since there are 9 individual single line and 2 is the no. of possible faults in each line (either stuck at 0 or 1). We can also try using fault collapsing to reduce the equivalent faults. To see more of fault collapsing, you can click here to read the post. Let's look at the truth table of the circuit to understand the stuck at faults more clearly,


From the truth table, we can see different input patterns can detect different stuck at 0/1 faults of different lines, and some faults can be detected by multiple patterns. The golden response or the expected output is denoted by y. We will create a stuck at 0/1 fault at each line and compare it with y to see if we can detect any faults. 

000 => cSA1, gSA1, hSA1, iSA1
001 => bSA1, cSA0, eSA1, fSA0, hSA0, iSA0
010 => aSA1, gSA1, hSA1, iSA1
011 => aSA1, bSA0, eSA0, fSA1,  gSA1, hSA1, iSA1
100 => bSA1, cSA1, dSA1, gSA1, hSA1, iSA1
101 => cSA0, eSA1, fSA0, hSA0, iSA0
110 => aSA0, dSA0, gSA0, iSA0
111 => aSA0, dSA0, gSA0, iSA0

As we can see pattern 001 and 011 has detected most faults so these two are an obvious choice. But only these two patterns can not detect all faults. We still need to detect aSA0, cSA1, dSA0, dSA1 and gSA0 faults. From the truth-table we can see 110 and 111 can detect the same faults. So, we can take any pattern we wish between them. Now for the remaining cSA1 and dSA1 fault we have to take pattern 100, because no other patterns can detect these two. 

So the patterns sets to detect all the stuck at faults are, {001, 011, 100, 110} or {001, 011, 100, 111} . 


See also: Test Generation and Fault Models

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