Test Generation And Fault Models

Test Generation

If the circuit under test (CUT) is an n input combinational logic circuit, we can apply all 2ⁿ possible input patterns for testing stuck-at faults; this approach is called exhaustive testing. It is time consuming and simply not practical. A more practical approach is to select specific test patterns based on circuit structural information and a set of fault models. This approach is called structural testing. It saves time and improves test efficiency.

Any input pattern or sequence of input patterns, that produces a different output response in a faulty circuit from that of the fault-free circuit is a test vector, or a sequence of test vectors, that will detect the faults. The goal of test generation is to find an efficient set of test vectors that detects all faults considered for that circuit. 

Fault Model

A representation of a “defect” at the abstracted function level is called a fault. Due to defect during manufacturing of integrated circuit, there is need to model the possible faults that might occur during fabrication process, this is called fault modelling.

Number of single faults = k X n

Number of multiple faults = (k + 1)ⁿ - 1

Where k = no. of possible faults and n = no. of input or output to the gate

Multiple fault model is a more accurate assumption that single fault model. But it is a much more complex model, so in practice we try to avoid it and do the single fault assumption model. Under the single fault model two or more faults may occur identical faulty behavior for all possible  input test patterns. These faults are called equivalent faults. The reduction of the entire set of single faults by removing equivalent faults is referred to as fault collapsing.

There are 2 X 9 = 18 possible faults under the single fault assumption since there are 9 individual single line and 2 is the no. of possible faults in each line (either stuck at 0 or 1).

No. of Collapsed faults = 2 X (no. of primary output + no. of fanout stems) + total no. of gate inputs (including inverters) - total no. of inverters) = 2 X (1 + 1) + 7 = 10

The minimum set of test vectors for 100% fault coverage for the circuit is 001, 011, 100 and 110. This is the efficient test vector that is generated to detect all faults. To understand how to get the efficient set of test vectors for this circuit you can read the What are Stuck At Faults In VLSI Digital Circuit Design post.  For detecting stuck at faults in sequential circuit we need to generate sequence of test vector. For this case, various DFT techniques are used. 

See also: Stuck at faults