Showing posts with the label VerilogShow all
Testbench for "4-bit Addition, But With A Twist" Problem | Verilog Code | VLSI

Testbench for "4-bit Addition, But With A Twist" Problem | Verilog Code | VLSI

June 27, 2022

To see the actual design problem, please go through the 4-bit Addition, But With A Twist post. Now we will write a simp…

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4-bit Addition, But With A Twist! | Verilog Code | VLSI

4-bit Addition, But With A Twist! | Verilog Code | VLSI

June 21, 2022

Question Take a random 8-bit input. The output is 5 bits [output sequence 4-bit and 1-bit extra]. If there are even num…

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Full Subtractor Verilog Code | VLSI

Full Subtractor Verilog Code | VLSI

December 04, 2021

Verilog Code: module full_sub (A, B, C, D, Borrow); input A, B, C; output D, Borrow; wire b1, b2; half_sub …

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Half Subtractor Verilog Code | VLSI

Half Subtractor Verilog Code | VLSI

December 04, 2021

Circuit of Half Subtractor: Verilog Code: module half_sub( A, B, D, Borrow); input A,B; output D, Borrow; assign …

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Eight Bit Adder | Verilog Code | VLSI

Eight Bit Adder | Verilog Code | VLSI

November 06, 2021

Block Diagram of an Eight Bit Adder: Here we will be making an eight  bit adder using 1 half-adder and 7 full-ad…

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