For What Faults Do We Have To Do Design For Testability (DFT)?

What is Design For Testability (DFT)?

Before understanding Design for Testability, we should know what is manufacturing defects. The term defect generally refers to a physical imperfection in the processed wafer. Some of the effects are observable through the optical or electron microscope. Others are not visible and can only detected by electrical tests. Philosophy of DFT is Murphy's law, "Whatever can go wrong, will go wrong". DFT is a structural technique, which facilitates a design to become testable after production, both in analog and digital design. Though it might not guarantee the accurate functionality of the logic, but it is our best bet yet.

Now, there are number of reasons why the output can differ from the golden response or the expected output. It’s because there are some faults induced. The agenda of this post is to talk about the faults that can occur in a design in the pre-silicon or post-silicon phase. 

Challenges In VLSI Testing

As the feature size and technologies are decreasing day by day, the design complexity and potential defects are increasing. The process variations affect transistor channel length, transistor threshold voltage, metal interconnect width and thickness and inter metal layer dielectric thickness will impact logical and timing performance. Random localized imperfections can result in resistive bridging between metal lines, resistive opens in metal lines, improper via formation etc. Nanometer scale devices are more susceptible to various types of noise with crosstalk and adversely affected by electro-migration and aging.

Types Of Fault For Which We Need To Do DFT

• Stuck at 0/1 faults
• Transistor faults
• Bridging faults
• Delay faults & crosstalk
• Transition delay faults
•  Coupling faults
• Address decoder faults