Partial Scan Design

Partial-scan design only requires that a subset of storage elements be replaced with scan cells and connected into scan chains. Depending on the structure of a partial-scan design, either combinational ATPG or sequential ATPG should be used.

In order to reduce the test generation complexity, many approaches have been proposed for determining the subset of storage elements for scan cell replacement. In the functional partitioning approach, a circuit is viewed as being composed of a data path portion and a control portion. Typically, because storage elements on the data path portion cannot afford too much delay increase, especially when replaced with Muxed-D scan cells, they are left out of the scan cell replacement process.

On the other hand, storage elements in the control portion can be replaced with scan cells. This approach makes it possible to improve fault coverage while limiting the performance degradation due to scan design.

In the pipelined or feed-forward partial-scan design approach, a subset of storage elements to be replaced with scan cells is selected to make the sequential circuit feedback-free. In order to select these storage elements, a structure graph is first constructed for the sequential circuit. For a feedback-free sequential circuit, the structure graph is a directed acyclic graph, where the maximum level in the structure graph is referred to as sequential depth. The sequential depth of a circuit is equal to the maximum number of clock cycles that must be applied in order to control and observe values to and from all non scan storage elements.

In a full-scan design, because all scan cells can be controlled and observed directly in shift mode, the sequential depth of a full-scan circuit is 0. Similarly, the sequential depth of a combinational logic block is also 0. In a partial-scan design, replacing a storage element with a scan cell is equivalent to removing its corresponding vertex from the structure graph.

In the balanced partial-scan design approach, a target sequential depth is used to further simplify the test generation process for the pipelined or feed-forward partial-scan design. In this approach, additional vertices are removed from the structure graph by replacing their corresponding storage elements with scan cells so the target sequential depth is met. By keeping the sequential depth under a small limit, one can apply combinational ATPG using multiple time frames to further increase the fault coverage of the design.

The main advantage of partial-scan design is that it reduces silicon area overhead and performance degradation. The main disadvantage is that it can result in lower fault coverage and longer test generation time than a full-scandesign.

See Also: Scan architecture, Full scan design, Muxed D scan cell, Random access scan design