Random Access Scan Design

In serial scan design, test pattern application & test response acquisition are both conducted serially through scan chains. Its major disadvantage is individual scan cells cannot be controlled or observed without affecting the values of other scan cells within the same scan chain. High switching activities at scan cells can cause excessive test power dissipation, resulting in circuit damage, low reliability, or even test-induced yield loss.

Random-access scan (RAS) attempts to alleviate these problems by making each scan cell randomly and uniquely addressable, similar to storage cells in a random-access memory (RAM). All Scan cells are organized into a 2D array for individual accessing. Random access capability is achieved by decoding a full address by a row decoder (X) & a column decoder (Y). A  log2n-bit address shift register, where n is the total number of scan cells, is used to specify which scan cell to access.

See Also: Scan architecture, Full scan design, Partial scan design, Muxed D scan cell