4-bit Addition, But With A Twist! | Verilog Code | VLSI

June 21, 2022

Question

Take a random 8-bit input. The output is 5 bits [output sequence 4-bit and 1-bit extra].

  • If there are even numbers of 1, the output is the addition of the first 4 bits with the last 4 bits.
  • If there are odd numbers of 1, the output is the addition of the first 4 bits with the gray code of the last 4 bits.

Design Criteria

  • Should be clock edge depended.
  • Reset is active low. 
  • Create instances of the adders for your design.  

Write a simple test-bench to check and validate your designed circuit with waveforms.

Answer

Binary to Gray Conversion

The MSB of a Gray code number is always the same as the first bit of the binary integer.

The exclusive-or (XOR) of the 1st and 2nd bits of the binary integer is used to conduct the 2nd bit of the gray code. All of the remaining bits are processed in the same way.



Code

// Code your design here


module verilog_test(
	out,
	val,
	clk,
	reset,
	enable
	);

    output	reg [4:0]	out;
	input		[7:0] 	val;
	input 				clk;
	input				reset;
	input				enable;
	wire		[7:0]	outvar;
    wire		[4:0]	tempA;
  	wire		[4:0]	tempB;
  	reg			[3:0]   cintA;
  	reg			[3:0]   cintB;
  
  initial 
  	begin
		out = 5'b00000;
	end
  	
  half_adder h1 (.A(val[4]), .B(val[0]), .S(tempA[0]), .C(cintA[0]));
  fulladder f1 (.A(val[5]), .B(val[1]), .Cin(cintA[0]), .S(tempA[1]), .Cout(cintA[1]));
  fulladder f2 (.A(val[6]), .B(val[2]), .Cin(cintA[1]), .S(tempA[2]), .Cout(cintA[2]));
  fulladder f3 (.A(val[7]), .B(val[3]), .Cin(cintA[2]), .S(tempA[3]), .Cout(cintA[3]));

  assign tempA[4] = cintA[3];	
			
  
  assign outvar[7] = val[7];
  assign outvar[6] = val[6];
  assign outvar[5] = val[5];
  assign outvar[4] = val[4];
  assign outvar[3] = val[3];
  assign outvar[2] = val[3]^val[2];
  assign outvar[1] = val[2]^val[1];
  assign outvar[0] = val[1]^val[0];

  half_adder h2 (.A(outvar[4]), .B(outvar[0]), .S(tempB[0]), .C(cintB[0]));
  fulladder f4 (.A(outvar[5]), .B(outvar[1]), .Cin(cintB[0]), .S(tempB[1]), .Cout(cintB[1]));
  fulladder f5 (.A(outvar[6]), .B(outvar[2]), .Cin(cintB[1]), .S(tempB[2]), .Cout(cintB[2]));
  fulladder f6 (.A(outvar[7]), .B(outvar[3]), .Cin(cintB[2]), .S(tempB[3]), .Cout(cintB[3]));

  assign tempB[4] = cintB[3];
  		
  always@ (posedge clk)
  	begin
    	if(~reset)
		begin
			out = 5'b00000;
		end

		else if(enable)
		begin
			if (~^val)
			begin
            	out = tempA;
            end
       
			else if(^val)
			begin
              out = tempB;
			end
		end
    end
endmodule

The half adders and full adders have been instantiated. 
To see the half adder code, click here.
To see the full adder code, click here.

To see the test-bench and simulation waveforms of the design, click here.


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