In the context of testability analysis, topology based methods like SCOAP and probability based methods are static in the sense that they do not use input test patterns. Typically these are very fast testability analysis methods in linear time but the accuracy is greatly reduced. On the other hand, simulation based methods are dynamic and uses input test patterns for testability analysis, also logic simulation and fault simulations can be employed.
In the simulation based testability analysis method, testability enhancement can be performed by statistical sampling in which a sample set of input test patterns are selected that are either gathered randomly or derived from a given pattern set, and logic simulation is conducted to collect the responses of all or part of signal lines of interest.
In addition to logic simulation, fault simulation has also been used to enhance the testability of a logic circuit using random or pseudo-random test patterns For example, a Random Resistant Fault Analysis (RRFA) method has been successfully applied to a high performance microprocessor to improve the circuits random testability in logic BIST.
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